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| Nuvacore has teased its WarpCore CPU IP |
In the high-stakes world of silicon design, a new challenger has emerged. Nuvacore, a startup founded by a trio of semiconductor veterans, is officially pulling back the curtain on its first general-purpose processor core. Codenamed WarpCore, this project is being spearheaded by Gerard Williams III, John Bruno, and Ram Srinivasan—names that carry serious weight in the CPU industry.
The founders aren't newcomers to the game. Williams, for instance, was a co-founder of Nuvia before Qualcomm acquired the company, and he previously honed his skills at Apple. Bruno and Srinivasan also bring deep experience from their time at Apple, Nuvia, and Qualcomm. The team recently strengthened its ranks by bringing in David Williamson, a former Apple CPU engineering leader, as Senior Vice President of Hardware Engineering.
A “Core First” Approach to CPU Design
So, what makes Nuvacore any different from the established giants? The company is now starting to explain what makes WarpCore unique. In an X post published on September 29, the company introduced what it calls a "Core First" development model.
Traditionally, CPU designers pick an instruction set architecture (ISA)—like x86 or Arm—and build the core around those specific rules. Nuvacore is turning that methodology on its head. Instead of choosing an ISA at the start of the project, they claim they can build much of the foundational CPU core IP first and select the ISA later, depending on the system it or one of its partners ultimately wants to build.
We said we planned to rewrite the rules of silicon. We meant it.
— NUVACORE (@NUVACOREAI) September 29, 2026
Today, we’re sharing the first details of our Core First approach. At NUVACORE, we can build a significant portion of the foundational CPU core IP before locking in an instruction set, giving our team the freedom… pic.twitter.com/Y5TJoAFdAH
Check out Nuvacore’s official X post here
This is a notable deviation from conventional CPU design methodology, where the target ISA typically shapes the design from the outset. Nuvacore says decoupling parts of the microarchitecture from the instruction set gives its engineers additional freedom to focus first on performance, power efficiency, and silicon area. The company has not yet said which ISA WarpCore will ultimately use. However, its hiring material references RISC-V, Arm64, and x86 as architectures relevant to its engineering work, suggesting that the underlying design is being developed with substantial ISA flexibility in mind.
Of course, it does not mean an instruction set can simply be bolted onto the core at the end. Decode, privilege levels, memory ordering, exception handling, and software compatibility still place major constraints on CPU design. With Nuvacore, enough of the performance-critical machinery can apparently be developed before the final ISA choice is locked down.
The Technical and Legal Hurdles
The company's job listings offer a few clues about what that foundational work includes. It is hiring engineers across branch prediction, instruction scheduling, register renaming, out-of-order execution, load/store design, cache and memory subsystems, coherence, and performance modeling. It is also recruiting for RTL, verification, and physical design roles, including work extending through tape-out and post-silicon correlation.
The legal side of the eventual ISA choice remains unresolved as well. RISC-V is comparatively straightforward because it does not require an Arm-style architecture license. An Arm implementation based on Nuvacore's own microarchitecture would require the appropriate Arm architecture rights somewhere along the way. Given Arm is in the business of selling CPU design IP, getting one could get tricky—more so with Arm's legal tiff with Qualcomm/Nuvia in the past. Lastly, x86 presents an even higher barrier because implementation rights are tightly controlled.
The Future of WarpCore
That raises another possibility: WarpCore may be intended as reusable CPU IP that partners with the relevant architectural licenses can adapt. The company itself has not yet clarified whether its long-term model will center on complete CPUs, licensable core IP, semi-custom silicon, or some combination of the three.
For now, critical details such as WarpCore's process node, cache hierarchy, pipeline configuration, vector capabilities, or tape-out schedule have not been revealed. However, the fact that it is deliberately keeping the ISA decision open makes this one of the more unusual clean-sheet CPU projects currently in development.